1. Field
This disclosure relates generally to semiconductors, and more specifically, to an integrated circuit having an electrostatic discharge (ESD) protection circuit.
2. Related Art
An integrated circuit (IC) may be subject to an electrostatic discharge (ESD) event that can damage the IC. Electrostatic discharge protection circuits include transistor clamps that are turned on in response to a fast rising transient voltage on an IC pin. The clamps are used to shunt ESD current between the power supply voltage rails and thereby protect the IC from damage. Typically, the clamps are implemented using relatively large metal oxide semiconductor field effect transistors (MOSFETs). A trigger circuit is used to detect the fast rising transient voltage and keep the clamp conducting for the duration of the ESD event. Thus, the trigger circuit typically includes a detection circuit and a timing control circuit. The detection circuit may include an RC (resistor-capacitor) “high pass” filter to differentiate between an ESD event and a regular power-up event, so that the trigger circuit does not turn on the clamp during the regular power-up event. Also, the timing control circuit may include a latch and positive feedback to hold the clamp in a full on condition for a specific amount of time to ensure that the clamp stays conductive during the entire duration of an ESD event. If the clamp is turned on during a false triggering of an ESD event the timing control circuit will ensure that the clamp will return to a non-conductive state within a relatively short amount of time to avoid excessive supply current and thermal damage of the clamp due to self-heating. False triggering of an ESD event can happen when the power supply voltage ramps up very quickly, or may happen in response to parasitic voltage spikes on the power supply.
FIG. 1 illustrates, in schematic diagram form, ESD protection circuit 10 in accordance with the prior art. ESD protection circuit 10 includes trigger circuit 11 and N-channel metal oxide semiconductor (NMOS) clamping transistor 20. Trigger circuit 11 includes detection circuit 12, current source 14, inverter 16, inverter 18, and polysilicon resistor 39. Detection circuit 12 includes PMOS capacitor 22 and NMOS resistor 24. Detection circuit 12 is implemented as an RC filter circuit for detecting a transient voltage on a power supply voltage terminal labeled “VDD”. Current source 14 includes PMOS transistors 26 and 30 configured as a current mirror and NMOS transistor 28. Inverter 16 includes PMOS transistor 32 and NMOS transistor 34. Inverter 18 includes PMOS transistor 36 and NMOS transistor 38. NMOS clamp transistor 20 is connected between VDD and a power supply voltage terminal labeled “VSS”. An output signal of second inverter 18 labeled “TRIGGER” is provided to control the gate of clamp transistor 20. Resistor 39 is connected between the gate of clamping transistor 20 and VSS. Not shown in FIG. 1 is the circuitry desired to be protected, such as for example, output drivers, input buffers, and other circuitry typically required for input/output (I/O) operation.
Detection circuit 12 monitors the voltage at VDD for an ESD event and turns on clamping transistor 20 when an ESD event is detected. During normal powered up operation with no detected transient voltage, node N1 at the output of detection circuit 12 is at a low level (VSS) and NMOS transistor 34 is turned off, or substantially non-conductive. The node TRIGGER at the gate of clamping transistor 20 is pulled low by resistor 39 causing transistor 20 to be off. Transistor 32 is on, causing a voltage at node N2 at the input of inverter 18 to be maintained at a high level (VDD). The state of inverter 18 is essentially latched by the action of transistors 32 and 34. The output of inverter 18 is low, thereby assisting resistor 39 in pulling the gate of transistor 20 at node TRIGGER to a low level. During an ESD event, detection circuit 12 detects a fast voltage increase on power supply rail VDD. The detected voltage increase causes the voltage at node N1 to be increased due to the gate capacitance of PMOS transistor 22 pulling node N1 high. The higher voltage at node N1 causes NMOS transistor 34 to be conductive. Node N2 at the input of inverter 18 is pulled low by NMOS transistor 34. Inverter 18 outputs a logic high signal to the gate of clamping NMOS transistor 20 at node TRIGGER, causing clamping NMOS transistor 20 to be conductive. In inverter 18, PMOS transistor 36 is a relatively large device to pull the signal at node TRIGGER up very quickly.
In order to achieve a reasonably long on-time of clamping transistor 20, inverter 18 remains latched for a predetermined time after node N1 returns to a low voltage and NMOS transistor 34 turns off. This is accomplished by the relatively high intrinsic gate capacitance of PMOS transistor 36 which functions to resist a rapid voltage change on node N2. The charging voltage for the large intrinsic gate capacitance is provided by current source 14 via the drain of PMOS transistor 30. Current source 14 is turned on only during an ESD event. The high trigger signal TRIGGER causes NMOS transistor 28 to be turned on, or made conductive. The drain current of NMOS transistor 28 is provided at node N2 via the current mirror formed by PMOS transistors 26 and 30. When detection circuit 12 no longer detects a rapidly changing transient voltage on VDD, the voltage at node N1 returns low, causing NMOS transistor 34 to be turned off. A relatively small current flow through PMOS transistor 30 maintains the gate capacitance of PMOS transistor 36 causing the voltage at node N2 to rise from a low to a high level whereas the time needed for this transition determines the on-time of the trigger circuit.
When the ramping voltage at node N2 reaches the switching point of inverter 18, inverter 18 changes states, causing the trigger signal at node TRIGGER to return to a logic low, thus turning clamping NMOS transistor 20 off. This completes the transitioning of the logic state of inverter 16 by turning on PMOS transistor 32 and pulling node N2 to VDD. The active feedback from node TRIGGER to inverter 16 via PMOS transistor 32 causes a very rapid turn-off (or de-latching) of trigger circuit 11. NMOS transistor 20 is relatively large to shunt current during the ESD event. If transistor 20 is turned off too quickly, a voltage spike may occur on the power supply line. The voltage spike may be caused by power supply inductance that resists a fast change in current flow.
FIG. 2 illustrates a diagram of various signals of ESD protection circuit 10 of FIG. 1. Note that the signals of FIG. 2 transition between a low voltage level labeled “L” and a high voltage level labeled “H”, where the low voltage level L may be ground (e.g. VSS) and the high voltage level may be a voltage level of a positive power supply voltage (e.g. VDD). As illustrated in FIG. 2, power supply voltage VDD is powered up at time T1. For illustration of clamp triggering and clamp turn-off behaviors of ESD protection circuit 10, a relatively fast power-up ramp is used to induce false triggering of an ESD event. The relatively fast transiting power up voltage causes the voltage at node N1 to increase and the voltage at node N2 to decrease. The voltage of trigger signal TRIGGER increases causing clamping transistor 20 to become conductive and shunt current to VSS. When the voltage at VDD stabilizes, the voltage at node N1 drops. When the voltage at node N1 drops sufficiently, transistor 34 becomes substantially non-conductive and the voltage at node N2 gradually increases. When the voltage at node N2 increases to the switching point of inverter 18, output voltage TRIGGER decreases rapidly, causing clamping transistor 20 to turn off, or become substantially non-conductive at time T2. The voltage of trigger signal TRIGGER is still relatively high when the logic state of inverter 18 changes. Clamping transistor 20 may turn off relatively fast causing a voltage spike on power supply voltage VDD as illustrated in FIG. 2. The voltage spike can also be seen in the waveforms of the voltages at nodes N1 and N2.
The advantages of using a latch in ESD protection circuit 10 include layout area efficiency and resilience to false triggering. However, due the inherent nature of a latch, the turn-off of the clamp transistor can happen very fast, thus causing voltage spikes due the power supply inductance. The voltage spikes can cause electrical overstress (EOS) damage in the IC. In some cases, the voltage spikes can cause re-triggering of the ESD protection circuit, which can put the IC into a state of repetitive ESD clamp turn-on cycles drawing continuous supply current. This may render the IC non-functional and may lead to overheating and failure of the IC.
Therefore, what is needed is an ESD protection circuit that solves the above problems.